2010.10.18

(一)

半加法器(Haif_adder)-Structural Model

(二)

半加法器(Haif_adder)-Verilog Behavioral Model

                                        (三)                                               

全加法器(Full_adder)

2010.10.11 2-bit 2 to 1 Mux

                                PS.此為2-bit  2 to 1 Mux之結果

2010.10.04 字串練習

Ex.2-1  (Simple Hello Module)

Ex.2-2  (Hello Module without White Space)

  Ex.2-3  (Hello Module with Extra White Space)

Ex.2-4  IIIegal Use of White Space

Ex.2-5  (Comments)